This invention relates to video display systems and more particularly to a system and methodology for synchronizing multiple video signals of multiple sources to compensate for time and processing delays of multiple video subsystems of the display system.
In a video display system having multiple video input sources or having a video input source which is processed and recombined with itself, the processing of the video data signal injects a finite time delay which could, if uncorrected, cause the resulting processed combinational video output signal to be erroneous and not the desired combinational result. For example, in the Video Explorer video processing system, from Intelligent Resources Integrated Systems, Inc., multiple video processing boards or systems can be interconnected by means of a video bus, each board being capable of receiving a separate input source and capable of providing a separate video output, both independent of the video bus. See copending U.S. patent application, Ser. No. 07/564,148, assigned to the assignee of the present invention, for details. In this system, there is a multiple pixel clock time delay between the video source input to a particular Video Explorer processing board system, and the output from that video processing system via its video bus connector. Where multiple Video Explorer processing board systems are coupled one to the next via the video bus, and where multiple external video input sources are connected, one to each board, the video processing system causes a time delay, between (1) the external video input video source to a subsequent video board and (2) the video data output from the previous video board coupled via the video bus as video data input, relative to the previous video board's external video source input. Thus, if multiple video processing boards are intercoupled, and combinationally process video signals through multiple video board systems, the results will be unacceptable as the various video inputs and processed intermediate results will be unsynchronized. Furthermore, where there are multiple video processing subsystems in the overall system, the delay added to the video source inputs by each subsequent board in the overall system, the delay increases cumulatively for all video processing delays introduced by previous video processing boards in the system. Prior solutions to video processing delay synchronization have been to utilize fixed or hard-wired delay lines or their equivalents. This is both inflexible, non-variable and for many applications ineffective. Additionally, it limits the flexibility and versatility of the overall video processing system.
It is therefore an object of the present invention to provide a video delay synchronization system for synchronizing multiple video processing subsystems which provides flexibility and adaptability for various functionality and delays.
It is a further object of the present invention to provide a time delay synchronization system for video signals which is selectively programmable and adaptable in real time.
It is a further object of the present invention to provide for an adaptive sychronization system for video signals which synchronizes external video sources with internal video bus signals to allow for their interactive combination and processing.
It is a further object of the present invention to additionally provide real-time programmable adaptive input masking.